It is known that different kinds of communication traffic are advantageously switched by means of different switching techniques. For example, the characteristics of voice communications are typically most compatible with circuit-switching techniques, while the characteristics of data communications are typically most compatible with packet-switching techniques.
When faced with switching of both voice and data traffic, the art has sought to provide the best-suited switching technique for each kind of traffic within a single switching system. An example thereof is U.S. Pat. No. 4,535,448, which discloses a single-node switching system having both a time-division multiplex (TDM) bus and a packet bus. Pulse-code modulated (PCM) voice signals are circuit-switched over the TDM bus between various ports that are connected to the TDM bus, while packetized data are packet-switched over the packet bus between the ports that are connected to the packet bus.
An advantage of the dual-bus system shown in this patent is that the packet bus permits efficient bandwidth utilization and high data rates. This is in contrast to a PCM-only switching system, which allocates bandwidth in fixed increments to data connections just like it does for voice communications, and maintains those allocations for the duration of the connections irrespective of actual use of the bandwidth. Hence, the dual-bus system uses bandwidth more efficiently and obtains higher throughput rates for a given bandwidth than the PCM-only system.
While the dual bus system shown in U.S. Pat. No. 4,535,448 provides efficient circuit-switching and packet-switching service for a single-node switching system, it offers no solution to the problem of transmitting both circuit-switched voice and packet-switched data between the various nodes of a multi-node switching system wherein each node thereof comprises, e.g., a switching system of the type shown in U.S. Pat. No. 4,535,448.
Arrangements for routing circuit-switched and packet-switched traffic between the nodes of a multi-node switching system are known. For example, U.S. Pat. No. 4,556,972 discloses an arrangement that provides for such interconnection by carrying both circuit-switched and packet-switched traffic between nodes in TDM circuit-switched form. However, the inter-node packet transmission capabilities of this system are not at the high data rates characteristic of packet buses. Instead, the inter-node packet transmission rate of this system is relatively low and is limited to that of a single system time slot. The reason for this is that this system serves inter-node packet communications by breaking up an inter-node packet into bytes and then transmitting the bytes one-by-one during successive occurrences, in successive transmission frames, of a time slot to which the packet transmission is assigned. The packet bytes are combined at the receiving end and reconstituted into a complete packet.
It can be seen that the system of this patent serves inter-node packet connections in the same manner as it serves inter-node voice connections. Namely, it serves both types of connections by assigning a single time slot to each such connection and by then transmitting the voice signals or data associated with the connection between the transmitting and receiving ends via the assigned time slot during successive occurrences of the time slot. This is the same manner in which the abovementioned PCM-only switching system handles intra-node voice and data transmissions. Consequently, the system disclosed in U.S. Pat. No. 4,556,972 fails to realize for inter-node transmissions the advantages that are offered for intra-node transmissions by the abovementioned system of U.S. Pat. No. 4,535,448.
The art has sought to introduce the advantages of high-speed packet data transfers to communication systems wherein inter-node transmissions of both circuit-switched and packetized traffic are accomplished by means of TDM facilities. For example, U.S. Pat. No. 4,731,785 discloses an arrangement for inserting circuit-switched and packetized traffic into different time slots of an inter-node TDM bus such that the circuit-switched traffic is carried by time slots of the TDM bus in a substantially conventional manner while packets are broken up into bytes and sequential bytes of a packet are inserted into sequential "idle" time slots of the TDM bus. "Idle" time slots are those that are not presently carrying circuit-switched traffic. "Idle" time slots are distinguished by the value of a special information bit that is inserted into each time slot, and which thereby specifies whether the traffic carried by the time slot represents circuit-switched or packetized traffic. The bytes of an inter-node packet may thus be carried by a plurality of time slots of a single transmission frame. This is in contrast to the system of U.S. Pat. No. 4,556,972, wherein the bytes of an inter-node packet are carried by only one time slot of a single frame. The arrangement of U.S. Pat. No. 4,731,785 thereby significantly increases the inter-node packet transmission rate to the full bandwidth of the TDM bus that is represented by the "idle" time slots.
While it does provide the requisite transmission rates for packetized traffic, U.S. Pat. No. 4,731,785 only discloses an arrangement for transporting integrated circuit-switched and packetized traffic between only two nodes. Unlike U.S. Pat. No. 4,556,972, it does not disclose a switching system network capable of interconnecting a plurality of endpoints, each one of which comprises a source of separate circuit-switched and packet-switched traffic, in a manner whereby the switching systems of the network are capable of routing individual communications, be they circuit-switched or packet-switched, to different individual ones of the endpoints. Rather, it discloses a switching network capable of interconnecting only two such endpoints and having no routing capability. And neither one of the patents offers any suggestions on how their respective advantages might be achieved within a single integrated circuit-and packet-switching network.
It is therefore a problem to provide a multi-node switching system having the capability of carrying and routing integrated inter-node circuit-switched and packet-switched traffic, with the packetized traffic being transmitted at the high data rates characteristic of packet switching systems.
A further difficulty is encountered in the area of capacity of the switching system to handle traffic growth. Traditionally, switch design has proceeded by first determining a maximum switch size, and then implementing a design that meets this size objective. Maximum designed switch size has often been based on the call-handling capacity of a feasible call control processor, and on engineered switch fabric capacity and switching bandwidth requirements. But once the switch design has been defined and the switch has been built, adding switching capacity beyond the predefined limit has been impossible, or very difficult at best.
It is therefore another problem to provide a multi-node switching system that avoids limitations on system growth, and that provides integrated circuit- and packet-switching bandwidth and capacity for as-yet unforeseen bandwidth-hungry applications and for unbounded line size growth--in other words, to provide a system that has a substantially-limitless growth architecture.
Certain switching fabric architectures do offer the possibility of substantially-limitless growth--the banyan network topology is a good example. However, most switching systems which are available today, irrespective of their switching fabric topology, are of the common control type. Common control systems, in general, comprise a switching fabric such as an array of crosspoints forming a network, and a centralized control which operates the fabric in order to establish a communication path. The centralized control typically has a maximum size expansion limit which is determined by the capacity of the control. Beyond a predetermined point, further size expansion requires replacement of the control, which generally requires total replacement by a different system. This also means that the total foreseeably-required control capacity must be provided right from the start, regardless of the line size of the system as initially implemented or put into service. Therefore, common control design is not economical for small-sized systems. And furthermore, even if the switching fabric itself is modularized and distributed, the number of control links required to connect the central control to all of the modules of a growing system quickly becomes prohibitively cumbersome and expensive.
In order to alleviate some of the problems associated with common control systems, the prior art has sought to develop control architectures that use distributed or progressive control. Distributed control systems, in general, comprise a number of switching stages which combine both control and switching in each stage. Since control and switching are provided in coordinated amounts, distributed control systems are economical at small line sizes and have virtually unlimited growth potential. Examples of distributed control systems are found in U.S. Pat. No. 3,860,761 which applies the distributed control concept to a space-division circuit switch, and in U.S. Pat. No. 4,488,288 which applies the concept to a banyan packet-switching network.
However, successful application of distributed control to other types of switches, such as time-division circuit switches and integrated circuit-and-packet switches, has heretofore been lacking. For example, a highly-touted attempt by a major international telecommunications equipment manufacturing company to develop a distributed-control TDM switch has been reported in the recent past to have failed drastically, after reported expenditures of over a billion dollars in development costs. It is therefore a further problem to provide a multi-node TDM switching system having distributed control, and particularly to provide a multi-node integrated circuit- and packet-switching system having distributed control.